Scopus
Article
1
A One-Dimensional Depthwise Separable Convolutional Neural Network for Bearing Fault Diagnosis Implemented on FPGA
Liang Y.P., Chen H., Chung C.C.
Sensors
2024, 24 (23)
Article
2
Implementation of Lightweight Convolutional Neural Networks with an Early Exit Mechanism Utilizing 40 nm CMOS Process for Fire Detection in Unmanned Aerial Vehicles
Liang Y.P., Chang C.M., Chung C.C.
Sensors
2024, 24 (7)
Conference Paper
3
A Low-Power Convolutional Neural Network Implemented in 40-nm CMOS Technology for Bearing Fault Diagnosis
Liang Y.P., Chang H.H., Chung C.C.
2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings
2024
Article
4
A Low-Power Hierarchical CNN Hardware Accelerator for Bearing Fault Diagnosis
Liang Y.P., Hsu Y.S., Chung C.C.
IEEE Transactions on Instrumentation and Measurement
2024, 73
Article
5
A Multiplier-Free Convolution Neural Network Hardware Accelerator for Real-Time Bearing Condition Detection of CNC Machinery
Liang Y.P., Hung M.Y., Chung C.C.
Sensors
2023, 23 (23)
Article
6
CNN Hardware Accelerator for Real-Time Bearing Fault Diagnosis
Chung C.C., Liang Y.P., Jiang H.J.
Sensors
2023, 23 (13)
Conference Paper
7
Lightweight CNN hardware accelerator using the ternary quantization method for fault diagnosis of CNC machinery
Chung C.C., Liang Y.P., Huang J.C.
2023 International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2023 - Proceedings
2023 , 133-134
Conference Paper
8
A Binary Weight Convolutional Neural Network Hardware Accelerator for Analysis Faults of the CNC Machinery on FPGA
Chung C.C., Liang Y.P., Chang Y.C., Chang C.M.
2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
2023
Article
9
A Maximum Logarithmic Maximum a Posteriori Probability Based Soft-Input Soft-Output Detector for the Coded Spatial Modulation Systems
Liu T.H., Jiang T.X., Chung C.C., Chu Y.S.
IEEE Transactions on Circuits and Systems I: Regular Papers
2022, 69 (9) , 3816-3828
Conference Paper
10
A Body Channel Communication Transceiver with a 16x Oversampling CDR and Convolutional Codes
Chung C.C., Tsai Y.T.
2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings
2022
學術著作
1
A low-power convolutional neural network implemented in 40-nm CMOS technology for bearing fault diagnosis
Yu-Pei Liang; Hui-Hsuan Chang; Ching-Che Chung
International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)
2024 年
4 月
International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)
研討會論文
2
A binary weight convolutional neural network hardware accelerator for analysis faults of the CNC machinery on FPGA
Ching-Che Chung; Yu-Pei Liang; Ya-Ching Chang; Chen-Ming Chang
International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)
2023 年
4 月
International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)
研討會論文
3
Lightweight CNN hardware accelerator using the ternary quantization method for fault diagnosis of CNC machinery
Ching-Che Chung; Yu-Pei Liang; Jo-Chen Huang
IEEE International Conference on Consumer Electronics – Taiwan (ICCE-TW)
2023 年
7 月
IEEE International Conference on Consumer Electronics – Taiwan (ICCE-TW)
研討會論文
4
A body channel communication transceiver with a 16x oversampling CDR and convolutional codes
Ching-Che Chung;Yi-Ting Tsai
International Symposium on VLSI Design, Automation, and Test (VLSI-DAT)
2022 年
4 月
International Symposium on VLSI Design, Automation, and Test (VLSI-DAT)
研討會論文
5
Using Quantization-Aware Training Technique with Post-Training Fine-Tuning Quantization to Implement a MobileNet Hardware Accelerator
Ching-Che Chung、Wei-Ting Chen、Ya-Ching Chang
Indo-Taiwan 2nd International Conference on Computing, Analytics and Networks (Indo-Taiwan ICAN)
2020 年
2 月
Indo-Taiwan 2nd International Conference on Computing, Analytics and Networks (Indo-Taiwan ICAN),pp.28-32
研討會論文
6
An all-digital built-in self-test circuit for ADPLLs in 65nm CMOS technology
Ching-Che Chung、Wei-Jung Chu、Yi-Ting Tsai
29th VLSI Design/CAD Symposium (VLSI CAD)
2018 年
8 月
29th VLSI Design/CAD Symposium (VLSI CAD),第-頁
研討會論文
7
FPGA-based accelerator platform for K-means clustering algorithm
Ching-Che Chung, Dai-Hua Lee and Yu-Hsin Wang
Annual Conference on Engineering and Applied Science (ACEAT)
2017 年
11 月
Annual Conference on Engineering and Applied Science (ACEAT),pp.41-50
研討會論文
8
A 0.52V/1.0V fast lock-in ADPLL for supporting dynamic voltage and frequency scaling
Ching-Che Chung, Wei-Siang Su and Chi-Kuang Lo
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2016 年
1 月
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,Vol.24, No.1,pp.408-412
期刊論文
9
A 1 Mb/s – 40Mb/s human body channel communication transceiver,
Ching-Che Chung, Chi-Tung Chang and Chih-Yu Lin
International Symposium on VLSI Design, Automation, and Test (VLSI-DAT)
2015 年
4 月
International Symposium on VLSI Design, Automation, and Test (VLSI-DAT),pp.-
研討會論文
10
An all-digital on-chip voltage sensor for SoC design
Ching-Che Chung, Mei-I Sun and Yi-Che Tsai
26th VLSI Design/CAD Symposium (VLSI CAD)
2015 年
8 月
26th VLSI Design/CAD Symposium (VLSI CAD),第-頁
研討會論文